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LTC3721-1 Push-Pull PWM Controller
FEATURES

DESCRIPTIO
High Efficiency Push-Pull PWM 1.5A Sink, 1A Source Output Drivers Adjustable Push-Pull Dead-Time Adjustable System Undervoltage Lockout and Hysteresis Adjustable Leading Edge Blanking Low Start-Up and Quiescent Currents Current Mode Operation Single Resistor Slope Compensation VCC UVLO and 25mA Shunt Regulator Programmable Fixed Frequency Operation to 1MHz Soft-Start, Cycle-by-Cycle Current Limiting and Hiccup Mode Short-Circuit Protection 5V, 15mA Low Dropout Regulator 16-Pin SSOP and (4mm x 4mm) QFN Packages
The LTC(R)3721-1 push-pull PWM controller provides all of the control and protection functions necessary for compact and highly efficient, isolated power converters. High integration minimizes external component count, while preserving design flexibility. The robust push-pull output stages switch at half the oscillator frequency. Dead-time is independently programmed with an external resistor. A UVLO program input provides precise system turn-on and turn off voltages. The LTC3721-1 features peak current mode control with programmable slope compensation and leading edge blanking. The LTC3721-1 features extremely low operating and start-up currents and reliable short-circuit and overtemperature protection. The LTC3721-1 is offered in 16-pin SSOP and (4mm x 4mm) QFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S

Telecommunications, Infrastructure Power Systems Distributed Power Architectures Server Power Supplies High Density Power Modules
TYPICAL APPLICATIO
VIN
Isolated Push-Pull Converter
VOUT
UVLO FROM AUXILIARY WINDING VCC DPRG VREF CT RLEB
DRVA DRVB CS RCS
LTC3721-1 VREF VOUT SS COMP VOUT V+ COLL COMP LT1431 RTOP RREF RMID
FB GND
GND-F GND-S
U
+
37211 TA01
U
U
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1
LTC3721-1
ABSOLUTE
AXI U RATI GS
VCC to GND (Low Impedance Source) .......- 0.3V to 10V (Chip Self-Regulates at 10.3V) UVLO to GND ............................................. - 0.3V to VCC All Other Pins to GND (Low Impedance Source) .........................- 0.3V to 5.5V VCC (Current Fed) ................................................. 40mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW VREF NC NC DRVB VCC DRVA GND CT 1 2 3 4 5 6 7 8 16 NC 15 UVLO 14 SS 13 FB 12 RLEB 11 COMP 10 CS 9 DPRG
UVLO
VREF
NC
LTC3721EGN-1
16 15 14 13 DRVB 1 VCC 2 DRVA 3 PGND 4 5 SGND 6 CT 7 NC 8 DPRG 17 12 FB 11 RLEB 10 COMP 9 CS
SS
ORDER PART NUMBER
GN PART MARKING 37211
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 100C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 9.5V unless otherwise noted.
SYMBOL Input Supply VCCUV VCCHY ICCST ICCRN VSHUNT RSHUNT SUVLO SHYST VCC Undervoltage Lockout VCC UVLO Hysteresis Start-Up Current Operating Current Shunt Regulator Voltage Shunt Resistance System UVLO Threshold System UVLO Hysteresis Current Measured on VCC Measured on VCC VCC = VUVLO - 0.3V No Load on Outputs Current into VCC = 10mA Current into VCC = 10mA to 17mA Measured on UVLO Pin, 10mA into VCC Current Flows Out of UVLO Pin, 10mA into VCC 4.8 8.5
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
2
U
U
W
WW U
W
(Note 1)
VREF Output Current ............................... Self-Regulated Operating Temperature (Notes 5,6) LTC3721-1 ......................................... - 40C to 85C Storage Temperature Range ................. - 65C to 125C Lead Temperature (GN Package only) (Soldering, 10sec) ............................................ 300C
TOP VIEW
ORDER PART NUMBER LTC3721EUF-1
UF PART MARKING 37211
UF PACKAGE 16-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 100C/W EXPOSED PAD IS GND (PIN17) MUST BE SOLDERED TO PCB
MIN
TYP 10.25
MAX 10.7 230 6 10.8 3.5 5.2 11.5
UNITS V V A mA V V A
3.8
4.2 145 3 10.3 1.4 5.0 10
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LTC3721-1
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 9.5V unless otherwise noted.
SYMBOL ROS IRMP ISLP DCMAX DCMIN DTADJ Oscillator OSCI OSCT OSCV VFB FBI AVOL IIB VOH VOL ISOURCE ISINK Reference VREF REFLD REFLN REFTV REFSC DRVH(x) DRVL(x) RDH(x) RDL(x) TDR(x) TDF(x) CLPP CLSD CLDEL SSI Initial Accuracy Load Regulation Line Regulation Total Variation Short-Circuit Current Output High Voltage Output Low Voltage Pull-Up Resistance Pull-Down Resistance Rise-Time Fall-Time Pulse by Pulse Current Limit Threshold Shutdown Current Limit Threshold Current Limit Delay to Output Soft-Start Current TA = 25C, Measured on VREF Load on VREF = 100A to 5mA VCC = 6.5V to 9.5V Line, Load and Temperature VREF Shorted to GND IOUT(x) = -100mA IOUT(x) = 100mA IOUT(x) = -10mA to -100mA IOUT(x) = -10mA to -100mA COUT(x) = 1nF COUT(x) = 1nF Measured on CS Measured on CS 100mV Overdrive on CS, (Note 2) SS = 2.5V 10 280 475
ELECTRICAL CHARACTERISTICS
PARAMETER Ramp Offset Voltage Ramp Discharge Current Slope Compensation Current Maximum Duty Cycle Minimum Duty Cycle Dead-Time Initial Accuracy VCC Variation CT Ramp Amplitude FB Input Voltage FB Input Range Open-Loop Gain Input Bias Current Output High Output Low Output Source Current Output Sink Current
CONDITIONS Measured on COMP, CS = 0V CS = 1V, COMP = 0V, CT = 4V Measured on CS, CT = 1V CT = 2.25V COMP = 4.5V COMP = 0V

MIN
TYP 0.65 50 30 68
MAX
UNITS V mA A A
Pulse Width Modulator
47
48.2 0 130
50
% % ns
TA = 25C, CT = 270pF VCC = 6.5V to 9.5V Measured on CT COMP = 2.5V, (Note 3) Measured on FB, (Note 4) COMP = 1V to 3V, (Note 3) COMP = 2.5V, (Note 3) Load on COMP = -100A Load on COMP = 100A COMP = 2.5V COMP = 2.5V
220 -3
250 2.35
280 3
kHz % V
Error Amplifier 1.172 - 0.3 70 4.7 400 2 4.925 90 5 4.92 0.27 700 5 5.00 2 1 4.900 18 5.000 30 9.2 0.17 2.9 1.7 10 10 300 600 80 13 16 320 725 5.075 15 10 5.100 45 0.5 50 1.2 1.22 2.5 V V dB nA V V A mA V mV mV V mA V V ns ns mV mV ns A
Push-Pull Outputs
Current Limit and Shutdown
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3
LTC3721-1
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 9.5V unless otherwise noted.
SYMBOL SSR FLT PARAMETER Soft-Start Reset Threshold Fault Reset Threshold CONDITIONS Measured on SS Measured on SS MIN 0.7 4.5 TYP 0.4 4.2 MAX 0.1 3.5 UNITS V V
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Includes leading edge blanking delay, RLEB = 20k, not tested in production. Note 3: FB is driven by a servo loop amplifier to control VCOMP for these tests. Note 4: Set FB to -0.3V, 2.5V and insure that COMP does not phase invert.
Note 5: The LTC3721-1 is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
TYPICAL PERFOR A CE CHARACTERISTICS
Start-Up ICC vs VCC
200
150
100
10.00
FREQUENCY (kHz)
ICC (A)
VCC (V)
50
0
0
2
4 VCC (V)
6
Leading Edge Blanking Time vs RLEB
350 300
5.00 5.05
250
BLANK TIME (ns)
VREF (V)
200 150 100
VREF (V)
50 0 0 10 20 30 40 50 60 RLEB (k) 70 80 90 100
372311 G04
4
UW
8
(TA = 25C unless otherwise noted) Oscillator Frequency vs Temperature
260 CT = 270pF
VCC vs ISHUNT
10.50
10.25
250
240
9.75
230
9.50
10
372311 G01
0
10
30 20 ISHUNT (mA)
40
50
372311 G02
220 - 60 - 40 - 20 0 20 40 60 TEMPERATURE (C)
80
100
372311 G03
VREF vs IREF
5.01
VREF vs Temperature
TJ = 25C
5.00
TJ = 85C 4.95
4.99
4.90 TJ = -40C 4.85
4.98
4.80 0 5 10 15 20 25 IREF (mA) 30 35 40
4.97 - 60 - 40 - 20 0 20 40 60 TEMPERATURE (C)
80
100
372311 G05
372311 G06
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LTC3721-1 TYPICAL PERFOR A CE CHARACTERISTICS
Error Amplifier Gain/Phase
190
100 80 60 40 20 0 -180 -270 -360 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M
GAIN (dB)
DELAY (ns)
ICC (A)
PHASE (DEG)
Slope Current vs Temperature
90 80 70 CT = 2.25V 10.5 10.4
FB VOLTAGE (V)
CURRENT (A)
60 50 40 30 20 10 0 -55 -25 5 35 65 TEMPERATURE (C) 95 125 CT = 1V
SHUNT VOLTAGE (V)
UW
(TA = 25C unless otherwise noted)
Start-Up ICC vs Temperature
275 250 225
Deadtime vs RDPRG
180 170 160 150 140 130 120 110 100 -55 -25 5 35 65 TEMPERATURE (C) 95 125
200k PREBIAS 200 175 150 125 100 75 50 0 50 100 150 200 250 300 350 400 450 500 RDPRG (k)
372311 G09
NO 200k PREBIAS
372311 G07
372311 G08
VCC Shunt Voltage vs Temperature
ICC = 10mA 1.205 1.204 1.203 1.202 1.201 1.200 1.199 1.198 -25 5 35 65 TEMPERATURE (C) 95 125
FB Input Voltage vs Temperature
10.3 10.2 10.1 10.0 9.9 9.8 -55
1.197 -55
-25
5 35 65 TEMPERATURE (C)
95
125
372311 G10
372311 G11
372311 G12
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5
LTC3721-1
PI DESCRIPTIO S
VREF (Pin 1/Pin 15): Output of the 5.0V Reference. VREF is capable of supplying up to 18mA to external circuitry. VREF should be decoupled to GND with a 1F ceramic capacitor. DRVB (Pin 4/Pin 1): High Speed 1.5A Sink, 1A Source Totem Pole MOSFET Driver. Connect to gate of external push-pull MOSFET with as short a PCB trace as practical to preserve drive signal integrity. A low value resistor connected between DRVA and the MOSFET gate is optional and will improve the gate drive signal quality if the PCB trace from the driver to the MOSFET cannot be made short. VCC (Pin 5/Pin 2): Supply Voltage Input to the LTC3721-1 and 10.25V Shunt Regulator. The chip is enabled after VCC has risen high enough to allow the VCC shunt regulator to conduct current and the UVLO comparator threshold is exceeded. Once the VCC shunt regulator has turned on, VCC can drop to as low as 6V (typical) and maintain operation. Bypass VCC to GND with a high quality 1F or larger ceramic capacitor to supply the transient currents caused by the high speed switching and capacitive loads presented by the on chip totem pole drivers. DRVA (Pin 6/Pin 3): High Speed 1.5A Sink, 1A Source Totem Pole MOSFET Driver. Connect to gate of external push-pull MOSFET with as short a PCB trace as practical to preserve drive signal integrity. A low value resistor connected between DRVA and the MOSFET gate is optional and will improve the gate drive signal quality if the PCB trace from the driver to the MOSFET cannot be made short. GND (Pin 7/Pin 4, Pin 5, Pin 17): All circuits in the LTC3721-1 are referenced to GND. Use of a ground plane is highly recommended. VIN and VREF bypass capacitors must be terminated with a star configuration as close to
6
U
U
(GN Package/UF Package)
GND as practical for best performance. For the 4mm x 4mm QFN package only, the internal power (PGND) and signal (SGND) buses are connected separately to pins 4 and 5 respectively, and the exposed pad must be soldered to PCB ground. CT (Pin 8/Pin 6): Timing Capacitor for the Oscillator. Use a 5% or better low ESR ceramic capacitor for best results. CT ramp amplitude is 2.35V peak-to-peak (typical). DPRG (Pin 9/Pin 8): Programming Input for Push-Pull Dead-Time. Connect a resistor between DPRG and VREF to program the dead-time. The nominal voltage on DPRG is 2V. CS (Pin 10/Pin 9): Input to Pulse-by-Pulse and Overload Current Limit Comparators, Output of Slope Compensation Circuitry. The pulse-by-pulse comparator has a nominal 300mV threshold, while the overload comparator has a nominal 600mV threshold. An internal switch discharges CS to GND after every timing period. Slope compensation current flows out of CS during the PWM period. An external resistor connected from CS to the external current sense resistor programs the amount of slope compensation. COMP (Pin 11/Pin 10): Error Amplifier Output, Inverting Input to Phase Modulator. RLEB (Pin 12/Pin 11): Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor connected between RLEB and GND to program from 40ns to 310ns of leading edge blanking of the current sense signal on CS for the LTC3721-1. A 1% tolerance resistor is recommended. The nominal voltage on RLEB is 2V. If leading edge blanking is not required, tie RLEB to VREF to disable.
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LTC3721-1
PI DESCRIPTIO S
FB (Pin 13/Pin 12): Error Amplifier Inverting Input. This is the voltage feedback input for the LTC3721-1. The nominal regulation voltage at FB is 1.2V. SS (Pin 14/Pin 13): Soft-Start/Restart Delay Circuitry Timing Capacitor. A capacitor from SS to GND provides a controlled ramp of the current command. During overload conditions, SS is discharged to ground initiating a softstart cycle. SS charging current is approximately 13A. SS will charge up to approximately 5V in normal operation. During a constant overload current fault, SS will oscillate at a low frequency between approximately 0.5V and 4V.
TI I G DIAGRA
DRVA DRVB
CURRENT SENSE OR CT RAMP PWM COMPARATOR (-)
37211 TD01
W
U
UW
U
(GN Package/UF Package)
UVLO (Pin 15/Pin 14): Input to Program System Turn-On and Turn-Off Voltages. The nominal threshold of the UVLO comparator is 5.0V. UVLO is connected to the main DC system feed through a resistor divider. When the UVLO threshold is exceeded, the LTC3721-1 commences a softstart cycle and a 10A (nominal) current is fed out of UVLO to program the desired amount of system hysteresis. The hysteresis level can be adjusted by changing the resistance of the divider. UVLO can also be used to terminate all switching by pulling UVLO down to less than 4V. An open drain or collector switch can perform this function without changing the system turn on or turn off voltages. NC (Pin 2, Pin 3, Pin 16/Pin 7, Pin 16): Not Connected.
PROGRAMMABLE DEAD-TIME
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7
LTC3721-1
BLOCK DIAGRA S
ERROR AMPLIFIER
SYSTEM UVLO VCC GOOD
FB
-
5V PULSE WIDTH MODULATOR
+ - -
14.9k
1.2V
+
50k
COMP
+
OSCILLATOR
+
650mV 1A SOURCE Q S R S 1A SOURCE DRVB 1.5A SINK FAULT LOGIC Q R T Q Q 1.5A SINK DRVA
-
+
VREF 13A
-
SS
+
SHUTDOWN CURRENT LIMIT
600mV
-
SLOPE COMPENSATOR
CS
BLANK
+
PULSE-BY-PULSE CURRENT LIMIT
RLEB
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300mV
-
GND
37211 BD01
W
8
LTC3721-1 Block Diagram
VREF CT DPRG 10A VCC REF GOOD 1.2V REF, LDO 5V
VCC
UVLO
VCC UVLO
10.25V "ON" 6V "OFF"
LTC3721-1
OPERATIO
Please refer to the detailed Block Diagram for this discussion. The LTC3721-1 is a PWM push-pull controller that operates with pulse-by-pulse peak current mode control. It is best suited for moderate to high power isolated power systems where small size and high efficiency are required. The push-pull topology delivers excellent transformer utilization and requires only two low side power MOSFET switches. The controller generates 180 out of phase 0% to < 50% duty cycle drive signals on DRVA and DRVB. The external MOSFETs are driven directly by these powerful on-chip drivers. The external MOSFETs typically control opposite primary windings of a centertapped power transformer. The centertap primary winding is connected to the input DC feed. The secondary of the transformer can be configured in different synchronous or nonsynchronous configurations depending on the application needs. The duty ratio is controlled by the voltage on COMP. A switching cycle commences with the falling edge of the internal oscillator clock pulse. The LTC3721-1 attenuates the voltage on COMP and compares it to the current sense signal to terminate the switching cycle. If the voltage on CS exceeds 300mV, the present cycle is terminated. If the voltage on CS exceeds 600mV, all switching stops and a soft-start sequence is initiated. A host of other features including an error amplifier, system UVLO programming, adjustable leading edge blanking, slope compensation and programmable dead-time provide flexibility for a variety of applications. Programming Driver Dead-Time The LTC3721-1 includes a feature to program the minimum time between the output signals on DRVA and DRVB commonly referred to as the driver dead-time. This function will come into play if the controller is commanded for maximum duty cycle. The dead-time is set with an external resistor connected between DPRG and VREF (see Figure 1). The nominal regulated voltage on DPRG is 2V. The external resistor programs a current which flows into DPRG. The dead-time can be adjusted from 90ns to 300ns with this resistor. The dead-time can also be modulated based on an external current source that feeds current into DPRG. Care must be taken to limit the current fed into DPRG to 350A or less. An internal 10A current source
U
sets a maximum deadtime if DPRG is floated. The internal current source causes the programmed deadtime to vary non-linearly with increasing values of RDPRG (see Typical Performance Characteristics). An external 200k resistor connected from DPRG to GND will compensate for the internal 10A current source and linearize the deadtime delay vs RDPRG characteristic.
VREF RDPRG OPTIONAL 200k DPRG
+
V 2V
+
2.5V
-
-
TURN-ON OUTPUT
37211 F01
Figure 1. Deadtime Adjust
Powering the LTC3721-1 The LTC3721-1 utilizes an integrated VCC shunt regulator to serve the dual purposes of limiting the voltage applied to VCC as well as signaling that the chip's bias voltage is sufficient to begin switching operation (under voltage lockout). With its typical 10.2V turn-on voltage and 4.2V UVLO hysteresis, the LTC3721-1 is tolerant of loosely regulated input sources such as an auxiliary transformer winding. The VCC shunt is capable of sinking up to 40mA of externally applied current. The UVLO turn-on and turnoff thresholds are derived from an internally trimmed reference making them extremely accurate. In addition, the LTC3721-1 exhibits very low (145A typ) start-up current that allows the use of 1/8W to 1/4W trickle charge start-up resistors. The trickle charge resistor should be selected as follows: RSTART(MAX) = VIN(MIN) - 10.7V/250A Adding a small safety margin and choosing standard values yields:
APPLICATION DC/DC Off-Line PFC Preregulator VIN RANGE 36V to 72V 85V to 270VRMS 390VDC RSTART 100k 430k 1.4M
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LTC3721-1
OPERATIO
VCC should be bypassed with a 0.1F to 1F multilayer ceramic capacitor to decouple the fast transient currents demanded by the output drivers and a bulk tantalum or electrolytic capacitor to hold up the VCC supply before the bootstrap winding, or an auxiliary regulator circuit takes over. CHOLDUP = (ICC + IDRIVE) * tDELAY/3.8V (minimum UVLO hysteresis) Regulated bias supplies as low as 7V can be utilized to provide bias to the LTC3721-1. Refer to Figure 2 for various bias supply configurations. Programming Undervoltage Lockout The LTC3721-1 provides undervoltage lockout (UVLO) control for the input DC voltage feed to the power converter in addition to the VCC UVLO function described in the preceding section. Input DC feed UVLO is provided with the UVLO pin. A comparator on UVLO compares a divided down input DC feed voltage to the 5V precision reference. When the 5V level is exceeded on UVLO, the SS pin is released and output switching commences. At the same time a 10A current is enabled which flows out of UVLO into the voltage divider connected to UVLO. The amount of DC feed hysteresis provided by this current is: 10A * RTOP, (Figure 3). The system UVLO threshold is: 5V * {(RTOP + RBOTTOM)/RBOTTOM}. If the voltage applied to
VIN 12V 10% 1.5k 1N5226 3V VBIAS < VUVLO 1N914 RSTART
VCC
Figure 2. Bias Configurations
ON OFF
Figure 3. System UVLO Setup
10
U
UVLO is present and greater than 5V prior to the VCC UVLO circuitry activation, then the internal UVLO logic will prevent output switching until the following three conditions are met: (1) VCC UVLO is enabled, (2) VREF is in regulation and (3) UVLO pin is greater than 5V. UVLO can also be used to enable and disable the power converter. An open drain transistor connected to UVLO as shown in Figure 3 provides this capability. Off-Line Bias Supply Generation If a regulated bias supply is not available to provide VCC voltage to the LTC3721-1 and supporting circuitry, one must be generated. Since the power requirement is small, approximately 1W, and the regulation is not critical, a simple open-loop method is usually the easiest and lowest cost approach. One method that works well is to add a winding to the main power transformer, and post regulate the resultant square wave with an L-C filter (see Figure 4a). The advantage of this approach is that it maintains decent regulation as the supply voltage varies, and it does not require full safety isolation from the input winding of the transformer. Some manufacturers include a primary winding for this purpose in their standard product offerings as well. A different approach is to add a winding to the output inductor and peak detect and filter the square wave signal (see Figure 4b). The polarity of this winding is designed so
VIN RSTART VCC
+
2k CHOLD
19211 F04a
+
1F VCC 1F CHOLD
37211 F02
15V*
1F
*OPTIONAL
Figure 4a. Auxiliary Winding Bias Supply
VIN LOUT VOUT
RTOP UVLO
RSTART
ISO BARRIER
+
RBOTTOM
1F
CHOLD
37211 F03
VCC
19211 F04b
Figure 4b. Output Inductor Bias Supply
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LTC3721-1
OPERATIO
that the positive voltage square wave is produced while the output inductor is freewheeling. An advantage of this technique over the previous is that it does not require a separate filter inductor and since the voltage is derived from the well-regulated output voltage, it is also well controlled. One disadvantage is that this winding will require the same safety isolation that is required for the main transformer. Another disadvantage is that a much larger VCC filter capacitor is needed, since it does not generate a voltage as the output is first starting up, or during short-circuit conditions. Programming the LTC3721-1 Oscillator The high accuracy LTC3721-1 oscillator circuit provides flexibility to program the switching frequency and slope compensation required for current mode control. The oscillator circuit produces a 2.35V peak-to-peak amplitude ramp waveform on CT. Typical maximum duty cycles of 49% are possible. The oscillator is capable of operation up to 1MHz by the following equation: CT = 1/(14.8k * FOSC) Note that this is the frequency seen on CT. The output drivers switch at 1/2 of this frequency. Also note that higher switching frequency and added driver dead-time via DPRG will reduce the maximum duty cycle. The LTC3721-1 derives a compensating slope current from the oscillator ramp waveform and sources this current out of CS. The desired level of slope compensation is selected with an external resistor connected between CS and the external current sense resistor, (Figure 5).
LTC3721-1 CT I= V(CT) 33k RSLOPE
33k
ADDED SLOPE CURRENT SENSE WAVEFORM
RCS
37211 F05
Figure 5. Slope Compensation Circuitry
Figure 6. Current Sense/Fault Circuitry Detail
+
CS
UVLO ENABLE
R
+
SWITCH CURRENT
650mV
-
SQ
-
-
U
Current Sensing and Overcurrent Protection Current sensing provides feedback for the current mode control loop and protection from overload conditions. The LTC3721-1 is compatible with either resistive sensing or current transformer methods. Internally connected to CS are two comparators that provide pulse-by-pulse and overcurrent shutdown functions respectively, (Figure 6). The pulse-by-pulse comparator has a 300mV nominal threshold. If the 300mV threshold is exceeded, the PWM cycle is terminated. The overcurrent comparator is set approximately 2x higher than the pulse-by-pulse level. If the current signal exceeds this level, the PWM cycle is terminated, the soft-start capacitor is quickly discharged and a soft-start cycle is initiated. If the overcurrent condition persists, the LTC3721-1 halts PWM operation and waits for the soft-start capacitor to charge up to approximately 4V before a retry is allowed. The soft-start capacitor is charged by an internal 13A current source. If the fault condition has not cleared when soft-start reaches 4V, the soft-start pin is again discharged and a new cycle is initiated. This is referred to as hiccup mode operation. In normal operation and under most abnormal conditions, the pulse-by-pulse comparator is fast enough to prevent hiccup mode operation. In severe cases, however, with high input voltage, very low RDS(ON) MOSFETs and a shorted output, or with saturating magnetics, the overcurrent comparator provides a means of protecting the power converter.
PULSE BY PULSE CURRENT LIMIT + CS 300mV - PWM PWM LATCH Q S UVLO PWM ENABLE LOGIC SQ R H = SHUTDOWN OUTPUTS Q RCS OVERLOAD CURRENT LIMIT + 4.1V 13A SS 0.4V CSS Q
37211 F06
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11
LTC3721-1
OPERATIO
Leading Edge Blanking The LTC3721-1 provides programmable leading edge blanking to prevent nuisance tripping of the current sense circuitry. Leading edge blanking relieves the filtering requirements for the CS pin, greatly improving the response to real overcurrent conditions. It also allows the use of a ground referenced current sense resistor or transformer(s), further simplifying the design. With a single 10k to 100k resistor from RLEB to GND, blanking times of approximately 40ns to 320ns are programmed. If not required, connecting RLEB to VREF can disable leading edge blanking. Keep in mind that the use of leading edge blanking will slightly reduce the linear control range for the pulse width modulator. High Current Drivers The LTC3721-1 high current, high speed drivers provide direct drive of external power N-channel MOSFET switches. The drivers swing from rail to rail. Due to the high pulsed current nature of these drivers (1.5A sink, 1A source), care must be taken with the board layout to obtain advertised performance. Bypass VCC with a 1F minimum, low ESR, ESL ceramic capacitor. Connect this capacitor with minimal length PCB leads to both VCC and GND. A ground plane
12
U
is highly recommended. The driver output pins (DRVA, DRVB) connect to the gates of the external MOSFET switches. The PCB traces making these connections should also be as short as possible to minimize overshoot and undershoot of the drive signal. Transformer Configurations The LTC3721-1 used in a typical isolated push-pull converter application will need a transformer to provide the voltage translation and galvanic isolation. The push-pull transformer employs a center tapped primary winding configuration. The transformer secondary can be center tapped or a single winding depending on the configuration and application needs. Center tapped secondary configurations apply alternating <50% duty cycle square waves to a single inductor/ capacitor combination. This L-C circuit filters the square wave and produces the regulated output voltage. The secondary square wave amplitude is given by: VSEC = VIN * N, where N = Ns/Np, transformer turns ratio, # of secondary turns divided by # of primary turns.
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LTC3721-1
OPERATIO
The duty cycle of these square waves is guaranteed to never exceed 50% by the LTC3721-1. In steady state operation, the duty ratio is given by: D = VOUT/(2 * VIN * N) To calculate the transformer turns ratio, first determine the minimum input voltage (VIN(MIN)) and the maximum duty ratio (D(MAX)) of the controller IC. This will be the worst case condition. An example is provided below: VIN = 32V to 75V, use VIN(MIN) = 30V to account for system voltage drops. VOUT = 7V Maximum duty cycle (DMAX) = 47% (per datasheet), use 45% for margin. The required transformer turns ratio is given by: Turns ratio (Ns/Np) = VOUT/(VIN(MIN) * 2 * D(MAX)) = 7V/(30V * 2 * 0.45) Ns/Np = (1/3.86)
U
Note that this is a simplified equation that does not take into account primary and secondary side voltage drops due to diodes, power MOSFETs, and resistive elements in the power paths. By margining down VIN(MIN) and DMAX as suggested above, the equation becomes closer to reality. An alternative secondary winding configuration uses a single non-center tapped winding and two filter inductors. Each end of the secondary winding alternately drives an inductor with <50% duty cycle square wave. The two inductors are connected together at the opposite ends to common output filter capacitor(s). This configuration is also called the current doubler rectifier. The current doubler utilizes half of the secondary windings compared to the center tapped case. The two out of phase inductors reduce the ripple current seen by the output and input capacitors, possibly allowing fewer capacitors in some applications. In addition, each output inductor carries half of the total load current, making them physically smaller, which can help to optimize the power stage layout. However, the total combined size may be slightly larger than the single inductor configuration.
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13
LTC3721-1
PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.254 MIN
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
23
4
56
7
8
.004 - .0098 (0.102 - 0.249)
.015 .004 x 45 (0.38 0.10)
.007 - .0098 (0.178 - 0.249) 0 - 8 TYP
.0532 - .0688 (1.35 - 1.75)
.016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
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LTC3721-1
PACKAGE DESCRIPTIO
4.35 0.05 2.15 0.05 2.90 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.115 TYP 0.55 0.20 15 16
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
UF Package 16-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 0.05 PACKAGE OUTLINE 0.30 0.05 0.65 BSC 1 2.15 0.10 (4-SIDES) 2
(UF) QFN 1103
0.200 REF 0.00 - 0.05
0.30 0.05 0.65 BSC
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LTC3721-1
TYPICAL APPLICATIO
VIN +VIN 1nF 200V C2, C3, C4, C5 4x33F 16V 5.1 1/2W 1nF 200V 5.1 1/2W 3 4 6
*
L1 22H 10 24V 9
*
*
12VIN
2xSi7370DP -VIN
1.21k 5V 73.2k 4.7 1/4W 330pF VIN 470 MMBT3904LT1 6 470 107k 15 UVLO CT RLEB 8 12 5 DRVA VCC 10 CS LTC3721EGN-1 GND FB 7 13 SS DPRG 14 9 4 DRVB FMMT718 FMMT718
EFFICIENCY (%)
1nF
1F D1 9.1V 100k 270pF 33k
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sn37211 37211fs
LTC3722-1/LTC3722-2 Dual Mode Phase Modulated Full-Bridge Controllers
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16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
U
COEV MGPWG-00001 EFD25 (1.28" x 1" x 0.504") 4T (42H) CT: 10T CT: 10T CT (PINS 1 TO 6, 7 TO 9, 11 TO 12) 1 * 11 C64 180pF 200V 160 2W 12 * MBRB20200CT 160 2W 180pF 200V +VS +VOUT
+
C6 56F 35V C8 0.1F 100V
4
3
C1 1F 100V
1
2
+
48V/3.65A C9 39F 100V -VOUT
-VS MBRB20200CT
2xSi7370DP
*
+
8 * R1 0.01 1.5W R2 0.01 1.5W 7 L2 22H
C7 56F 35V
T2 0.59mH PULSE P0353
92 10.6VIN 91 13.2VIN 12VIN 90
4.7 1/4W
89
1.5k 1/4W
24V +VS
88
1.0
1.5
2.0 2.5 3.0 LOAD CURRENT (A)
3.5
4.0
1k COMP VREF 1 1.2k 10k 5 C10 2.2nF 250V 2 D2 9.1V 100k 1 11 6 3 V+ 2 1 MOC207 10nF
2k 46.1k 10k 1nF 100V 8
NOTES: T2, C1, C9 ARE OPTIONAL AND REDUCE OUTPUT RIPPLE TO LESS THAN 50mVP-P. 10mA MINIMUM LOAD REQUIRED. START VOLTAGE 10.8V MAX. C2-C5: TDK C4532X7R1336M (1812) C10: MURATA DE2E3KH222MB3B C1: TDK C3225X7R2A105M (1210) C6, C7: SANYO 35MV56WX C9: SANYO 100MV39AX C8: TDK C3216X7R2A104M (X7R 1206) D1, D2: MMBZ5239B R1, R2: IRC LRC-LR2512-01-R010-G L1, L2: TDK SLF12575T-220M4R0
37211 TA02
4
COMP RTOP LT1431CS8 COLL REF GND-F GND-S RMID 6 5 7
68nF
1F
1.5nF
2.49k
-VS
LT/TP 0504 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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